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| SPICE Device Model SUD50N02-06P Vishay Siliconix N-Channel 20-V (D-S) 175 MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70104 08-Jun-04 www.vishay.com 1 SPICE Device Model SUD50N02-06P Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current b Symbol Test Conditions Simulated Data 1.4 964 0.0041 0.0057 0.0065 0.91 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = 250 A VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 20 A V A 0.0046 0.0073 1.2 V Drain-Source On-State Resistanceb rDS(on) VGS = 10 V, ID = 20 A, TJ = 125C VGS = 4.5 V, ID = 20 A Forward Voltageb VSD IS = 50 A, VGS = 0 V Dynamic a Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Charge Gate-Drain Chargec Turn-On Delay Timec Rise Time c c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr IF = 50 A, di/dt = 100 A/s VDD = 10 V, RL = 0.20 ID 50 A, VGEN = 10 V, RG = 2.5 VDS = 10 V, VGS = 4.5 V, ID = 50 A VGS = 0 V, VDS = 25 V, f = 1 MHz 2418 816 348 20 7.5 6 11 10 9 9 31 2550 900 415 19 7.5 6 11 10 24 9 35 ns nC pF Turn-Off Delay Timec Fall Timec Source-Drain Reverse Recovery Time Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 300 s, duty cycle 2%. c. Independent of operating temperature. www.vishay.com 2 Document Number: 70104 08-Jun-04 SPICE Device Model SUD50N02-06P Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70104 08-Jun-04 www.vishay.com 3 |
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